Fault detecting device for multiplex signal transmission system

ABSTRACT

There is provided a fault detecting device for a multiplex signal transmission system which comprises a fault detecting circuit, whereby when a fault occurs in the level signal line for sending load actuating command signals in a multiplex signal transmission system operated in a time-shared manner, the fault detecting circuit generates a signal for preventing the actuation of the loads due to the fault.

U it tates Ptent 1 1 1 1 M Akita Nov. 2% W74 TAIULT DETECTING DEVICE FOR3,696,210 10/1972 Peterson 179/15 BF MULTHPLEX SIGNAL TRANSMISSHON3,717,863 2/1973 Kempen 340/253 R SYSTEM Inventor: Sigeyulti Altita,Kariya, Japan Nippon Solten, lino, Nishio-shi, Aichi-ken, Japan Oct. 4,1973 Assignee:

Filed:

Appl. No.1

Foreign Application Priority Data Oct. 5, 1972 Japan 47-100481 us. c1179/115 BF Hm. c1. 1111114 3/14 Field of Search 179/15 BF, 69 0;

References Cited UNlTED STATES PATENTS 1 1/1957 Gerks 340/253 A PrimaryExaminer-Ralph D Blalteslee Attorney, Agent, or Firm-Cushman, Darby &Cushman 3 Claims, 49 Drawing Figures LATOR FIRST I COUNTING 3 BLOCSOURCE I POWER llO 3 COMBINING BLOCK 5N SECOND 1 COUNTING BLOCK I l lRESTORING CIRCUIT Limo ll II ll FIG. I

. OSCIL- FlRST 'LATOR COUNTING BLOCK I I0 I i 3 COMBINING BLOCK 2 IPOWER 1 SOURCE sum 03% 11 FIG. 3

HO I300 0-9 MID-o I40 x mmlm 4111mm FREQUENCY SCALE-OF I SCALE-OFOSCILLATOR DIVIDER IO ID CIRCUIT COUNTER X COUNTER 5 I30 I3I I40 T -|22LOGIC INANDI CIRCUIT GENERATING CIRCUIT PATENTEL HOV 2 6 I874 sum as (1F11- PATEmmmsmm 3,851I1O7 sum 070F11 FIG. 10

|||||||||P- Hummi- FREQUENCY f S- Q g UNDER 7 COUNTER COUNTER S s, I80I30 I40 LOGIC CIRCUIT i \lwo RESET PULSE GENERATING CIRCUIT I I52 I50 Ik k g M5 O' O o C I23 l I PAIENIEDIIUVEBISH 3.851 .107

sum 0s 0F 11 I FAULT DETECTING LOAD CIRCUIT PATENTELIIUVZBW Y 3 51.107

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Pmmu W2 4 3.851 ,107

7} LOAD H I l) F| |7 Q; II H IF H H INF- IN FIG. we; LFLH M n rL---nr-FIG. 170g" r U Fae. I702 i n [1 FIG. I7EC') I FIG. WP}; n W' FIG. We! uFIG. 17H}; u

we. mg" F FAULT DETECTING DEVICE FOR MULTIPLEX SIGNAL TRANSMISSIONSYSTEM BACKGROUND OF THE INVENTION IELD OF THE INVENTION The presentinvention relates to a fault detecting de vice for a multiplex signaltransmission system comprising a transmitter and a receiver andemploying a multiplex communication method based on time-sharing.

SUMMARY OF THE INVENTION It is the object of the present invention toprovide a fault detecting device for a multiplex signal transmissionsystem which detects the occurrence of a fault in the level signal linefor sending load actuating command signals and prevents the actuation ofthe loads due to the fault.

A remarkable advantage of the device of the present invention is the useof a fault detecting circuit in a multiplex signal transmission systemcomprising a transmitter and a receiver and employing a multiplexcommunication method based on time-sharing with the result that when afault occurs in the level signal line for send? ing load actuatingcommand signals, the fault is detected to prevent the actuation of allthe loads due to the fault.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram showing anembodiment of 0 generating circuit shown in FIG. 3.

FIGS. 6A and 6B are input and output characteristic diagrams of thereset pulse generating circuit shown in FIG. 5.

FIG. 7 is an electric circuit diagram showing in detail the internalcircuit of the first counting block shown in FIG. 3.

FIG. 8 is a block diagram showing a part of the combining block shown inFIG. 1.

FIG. 9 is an electric circuit diagram of the whole combining block shownin FIG. 1.

FIG. 10 is a block diagram of the second counting block shown in FIG. 1.

FIG. 11 is an electric circuit diagram showing a part of the restoringblock shown in FIG. 1.

FIG. 12 is an electric circuit diagram of the whole restoring blockshown in FIG. 1.

FIG. 13 is a block diagram of the multiplex signal transmission systemincorporating two receivers.

FIG. 14 is an electric circuit diagram showing-an embodiment of thefault detecting. circuit used in the device of this invention..

FIGS. 15A to 15C are waveform diagrams useful for explaining theoperation of the fault detecting circuit shown in FIG. 14.

FIG. 16 is an electric circuit diagram showing another embodiment of thefaultdetecting circuit in the device of this invention.

FIGS. 17A to 171 are waveform diagrams useful for explaining theoperation of the fault detecting circuit shown in FIG. 16.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will bedescribed hereunder with reference to the illustrated embodiments.

An embodiment of a time-sharing multiplex signal transmission systemincorporating the device according to the present invention will bedescribed first with reference to FIGS. 1 to 13.

In FIG. 1, which shows a block diagram of the overall device accordingto the invention, a transmitter I is constituted of a first countingblock 2, a combining block 3 and an oscillator 110, while a receiver 4consists of a second counting block 5 and a restoring block 6, and apower source 7 may be, for example, an accumulator. The generaldescription of the time-sharing multiplex signal transmission systemincorporating the device according to the present invention shown inFIG. 1, will now be described by reference to the waveforms shown inFIGS. 2A to 21. The time base indicated at 101 in FIG. 2D is dividedinto equal periods, each comprising smaller intervals 00, 01, 02, 99,and signals to be transmitted to the receiving end are allotted to theintervals. The receiver discriminates whether the intervals contain thecorresponding signals or not and picks up the predetermined ones of thesignals only when they are contained in the respective intervals. Thistime-sharing process is performed on the basis of a synchronous signalindicated at 123 in FIG. 2B and delivered from the first counting block2 and a timing signal 122 indicated at 122 in FIG. 2A, through theprovision of the scale-of-IO counters in the counting blocks 2 and 5respectively of the transmitter l and the receiver 4. These scale-0H0counters generate an address signal corresponding to the thus definedintervals, i.e. time-shared intervals. The signals to be transmitted arecombined together through the combining block 3 to produce a levelsignal indicated at 124 in FIG. 2C, which is transmitted from thecombining block 3. Therefore, the signal transmission between thetransmitter 1 and the receiver 4 is through three lines, i.e. line L,for the synchronous signal 123, line L for the timing signal 122 andline L for the level signal 124, while two additional lines L and L areprovided therebetween for the purpose of power feeding. The synchronoussignal 123 in which a. period corresponding in time to the time-sharedinterval 00 has a lower level, is transmitted from the counting block 2to the counting block 5. A reset signal 151 shown in FIG. 2H is obtainedfrom a signal indicated at 161 in FIG. 26 in which a periodcorresponding to the time-shared interval 00 has a higher level. And thereset signal 151 resets frequency dividers and the scale-of-IO countersin the counting blocks 2 and 5. Each time-shared interval is supersededby the succeeding one every second period of the timing signal 122.Thus, the scale-of-l0 counters provided in the counting; blocks 2 and 5are operated all in synchronism. The level signal 124 to be transmittedfrom the transmitter I to the receiver 4 is obtained by passing, i.e.taking a logical product of, three signals; a predetennined input signalto be transmitted, an address signal from the scale-of-ll countercontaining addresses indicative of the numeral-pairs (such as 02 or 04)of the time-shared-intervals into which theinput signal is allotted, anda strobe signal indicated at 181 in FIG. 2E; through an AND gate. Thelevel signal 124 shows a case where a signal to be transmitted issuperposed on the addresses in the timeshared intervals indicated by thenumeral-pairs 01 and 02. This level signal 124 is then restored throughthe restoring block 6 in the receiver 4 in the manner described below.The initial state is established by applying the reset signal 151 shownin FIG. 2H to the reset input of a first memory circuit during thetime-shared interval 00. Then, an output signal which is the logicalproduct of the address signal appearing in the predetermined time-sharedintervals and the level signal 124, is applied to the set input of thefirst memory circuit. Therefore, if an AND signal is applied to the setinput the initial state of the memory circuit is cleared, while theinitial state is maintained if there is no input to the memory circuit.Namely, the state of the first memory circuit is determined dependingupon whether there is a level signal in respective time-shared intervalsor not. The state is again cleared when the following timesharedinterval 00 has been reached and it is necessary to transfer the contentof the first memory to a second memory circuit before the former iscleared. This transfer operation is performed during the time-sharedinterval 99 by applying a transfer signal 171 shown in FIG. 2F, which isthe logical product or AND of the interval 99 and the strobe signal 181in FIG. 2E, to a gate which controls the transmission of the signalbetween the first and second memories. If in signal 124 a predeterminedsignal is in the interval 01 (or has a lower level in the interval), thecontent of .the first memory is continuously fed to and stored in thesecond memory during the duration of a signal 191 shown in FIG. 2I fromthe time-shared interval 99 in a period to the interval 99 in the nextperiod. If, on the other hand, in the signal 124 a predetermined signalis in the interval 02, the transfer of the content takes place in asimilar manner, but during the duration of a signal .192 shown in FIG.2] with a delay of one period with respect to the signal 191. Therefore,if in the level signal 124 a predetermined signal appears in everyinterval 01, the signal 191 will last without interruption from theinterval 99 shown in FIG. 21 onward.

Now, the signal transmission according to the timesharing system will bedescribed with a detailed description of the circuit constitutions ofthe essential blocks. FIG. 3 shows the constitutions of the oscillator110 and the first counting block 2 in the transmitter 1. The oscillator110 may be constituted of a tuning fork and quartz or have resort to acapacitor-resistor compensated feedback method. In the first countingblock 2, the n-th output 121 and (n-l )th output 122 (timing signalshown in FIG. 2A) of the n-th stage of a frequency divider circuit 120are applied to a logic circuit 180, which takes the NAND of the outputs.The output of the NAND circuit 180 is then fed to an inverting gate 182,which in turn delivers the strobe signal 181. The strobe signal 181 isused to prevent the interference of the signals indicative of thetime-shared intervals in transmission and reception. The logic circuit180 may be substitutedby an OR ELSE circuit which takes the exclusivelogic sum of the signals 121 and 122. Reference numerals 130 and 140indicate scale-of-10 counters. The scale-of-l0 counter must be a devicewhich delivers at its output terminals 130-0 to 130-9 output signalshaving waveforms as shown in FIG. 4. This requirement can be satisfiedby using the well known MOS IC CD4017D manufactured by RCA or by acombination of suitable gates. FIG. 4A shows an output signal 121frequency divided by the frequency divider circuit 120, FIG. 4B shows areset signal 151 which is an output of a reset pulse generating circuit150 described below, FIGS. 41C to 4L show signals delivered respectivelyfrom the output terminals 130-0 to 130-9 of the scale-of-ll0 counter130, and FIG. 4M shows an output signal 131 from the counter 130. Thesignal 131 from the counter 130 indicating the digit of the first placeof the numeral-pair representing the time-shared interval, is applied tothe scale-of-10 counter which delivers an output signal indicating thedigit of the second place of the same numeral-pair. The scale-of-ll0counter 140 operates in the same manner as the counter 130. The signalsderived respectively from the output terminals 130-0 and 140-0 of thecounters 130 and 140 are fed to an AND gate 160, the output of which isthen applied to an inverting gate 162 to obtain a synchronous signal 123at its output terminal. The reset pulse generating circuit receives theoutput signal 161 of the AND gate as its input signal, and an embodimentof the circuit 150 is illustrated in FIG. 5. In FIG. 5, the reset pulsegenerating circuit 150 comprises an AND gate 150a, inverting gates 150bto 150d, an input terminal 150e and an output terminal 150f. When theoutput signal 161 of the AND gate 160 whose waveform is shown in FIG. 6A(identical with that shown in FIG. 2G), is applied to the input terminal150e, then at the output terminal 150f appears the reset signal 151shown in FIG. 6B (identical with that shown in FIG. 211). The resetsignal 151 as the output of the reset pulse generating circuit 150 isapplied to the reset terminals of the frequency divider circuit 120 andthe scale-of-10 counters 130, 140, respectively.

It is assumed in the following description that the frequency dividercircuit 120 has a dividing factor equal to half a bit and that the (n-l)th output of the circuit 120, i.e. output of the oscillator 110, isused as the timing signal 122. CD42l7D FIG. 7 shows a concreteembodiment of a circuit shown in a block diagram in FIG. 3. In FIG. 7,the descriptions of the already mentioned circuit elements are abridged.The oscillator 110 has a well known constitution comprising invertinggates 1100, 110b and 110:, a resistor 110d and a capacitor 110e. Thefrequency divider 120 comprises a flip-flop 120a and an inverting gate.The scale-of-10 counter 130 is the above-mentioned, well-known MOS ICCD4217D by RCA, which comprises D flip-flops 130a to 130e, negativelogic AND gates 130f to 130p, a NOR gate 130q and an inverting gate130r. The scale-of-10 counter 140 has the same constitution and operatesin the same manner as the counter 130. The logic circuit 180 is a NANDgate 180a. An AND gate and an inverting gate 152 in the unit shown inFIG. 7 are useful only where the unit is used for the second countingblock 5 in the receiver 4 but useless where the unit is used for thefirst counting block 2 in the transmitter 1. These elements areincorporated together with other circuit elements in a single lC unit orpackage and, therefore, if the unit is used for the first counting block2 of the transmitter 1, the AND gate 170 and the inverting gate 152 areleft out of electrical connection.

FIG. 8 shows a part of the combining block 3 of the transmitter 1,having a constitution for one channel associated with one address. Theterminals 211 and 212 are connected respectively with the selected oneof the terminals 130-0 to 130-9 of the scale-of-10 counter 130 and theselected one of the terminals 140-0 to 140-9 of the scale-of-ll counter140 so as to obtain an address representative of a predeterminedtime-shared interval. For example, in order to obtain an addressindicating the time-shared interval 13, it is only necessary to connectthe terminal 211 with the output terminal 140-1 of the counter 140associated with the digit of the second place of the numeral-pairrepresenting the timeshared interval and the terminal 212 with theoutput terminal 130-3 of the counter 130 associated with the digit ofthe first place of the numeral-pair representing the time-sharedinterval. Such connections are represented for simplicitys sake by adashed line in FIG. 1 connecting the first counting block 2 with thecombining block 3. A terminal 220 is an input terminal which receives asignal transmitted from the transmitter 1 to the receiver 4 and aninverting gate 221 is provided to deliver the inversion of the inputsignal. The NAND gate 240 takes the NAND of the signals applied to theterminals 211 and 212 and the signal delivered from the inverting gate221. Namely, the gate 240 delivers a low-leveled, 0 signal only whenthere are applied to the gate 240 a predetermined address signal and aninput signal corresponding to the address. The output of the NAND gate240 together with the outputs of the other NAND gates similar to theNAND gate 240 which are associated with the other addresses, is appliedto a NAND gate 250. This state is, for example, illustrated in FIG. 9. ANAND gate 260 takes the NAND of the output signal from the NAND gate 250and the strobe signal 181 and delivers the level signal 124 to the lineL The combining block 3 shown in FIG. 9 is adapted for receiving teninputs, i.e. ten channels, corresponding to ten addresses.'I-Iowever,if, as described later, the receiver 4 has eight input terminals, onlyeight channels out of ten are used for signal transmission. Theselection of any address corresponding to each of the time-sharedintervals 00 to 99 can be made by appropriately combining the outputs ofthe scale-of- 10 counters 130 and 140. The number of channels for signaltransmission in this embodiment is not limited to eight but may beincreased up to 98, if need be, since there are ninety-eight time-sharedintervals 01 to 98.

As described above, in signal transmission, any one of the addressescorresponding to the time-shared intervals 00 to 99 can be arbitrarilyselected by means of the counting block 2 and the combining block 3.

Now, the constitution and the operation of the receiver 4 will bedescribed. The receiver 4 comprises the restoring block 6 and the secondcounting block similar to the counting block 2 shown in FIG. 7 but witha somewhat different'connection. FIG. 10 illustrates in detail theconstitution of the counting block 5 for use in the receiver 4. Thefrequency divider circuit 120' is actuated by the timing signal 122which is received from the first counting block 2 in the transmitter 1through the line L,;,. The reset pulse generating circuit 150' receivesthe output of an inverting gate 152 (see FIG. '7) which inverts thesynchronous signal 123 fed through the line L The signals appearing atthe output terminal l30'-9 of a scale-of-10 counter 130" associated withthe digit of the first place of the numeral-pair representing thetime-shared interval and at the output terminal l40-9 of a scale-of-10counter 140' associated with the digit of the second place of the samenumeral-pair, and the strobe signal 181 are applied to an AND gate 170to produce the transfer signal 171. With the circuit configurationdescribed above, the scale-of- 10 counters 130' and 140 operate insynchronism with the transmitting end.

The circuit of the second counting block 5 in the receiver 4 is the sameas that of the first counting block 2 in the transmitter 1 in FIG. 7,but the NAND gate 160 and the inverting gate 162 shown in FIG. 7 areunnecessary for the operation of the second counting block 5 and theyare omitted in the circuit shown in FIG. 10. The frequency dividercircuit the scale-of-l0 counters and the reset pulse generating circuitand the logic circuit of the second counting block 5 in the receiver 4have the same constitutions and operate in the same manner as those ofthe first counting block 2 in the transmitter 1 in FIG. 7.

FIG. 11 shows the electrical connection of one of the constituents, i.e.equivalent components, of the restoring block 6. NAND gates 310 and 320form a setreset type flip-flop serving as a first memory circuit. NANDgates 360 and 370 also form a set-reset type flip-flop serving as asecond memory circuit. Numeral 400 designates a fault detecting circuit.This unit receives the strobe signal 181 and the transfer signal 171from the second counting block 5 shown in FIG. 10 and has terminals 211'and 212"which are adapted to receive an address signal representing atime-shared interval. For example, if the terminals 211 and 212' areconnected respectively with the output terminal 140'-1 of thescale-of-10 counter 140 and the output terminal 130'-3 of thescale-of-10 counter 130', an address signal indicative of thetime-shared interval 13 is introduced to the unit. These connections arerepresented for simplicitys sake by a dashed line between the secondcounting block 5 and the restoring block 6 in FIG. 1. The operation ofthe unit is as follows. The first memory circuit assumes its initialstate upon reception of the reset signal 151 from the second countingblock 5 to maintain the output terminal 311 at a higher level and theoutput terminal 321 at a lower level and this state continues after thereset signal 151 has ceased. If, for example, the address signalrepresenting the interval 13 is applied from the counters 130' and 140'respectively to the terminals 211 and 212' while at the same time thelevel signal 124 applied to the unit through the line L has the higherlevel allocated to the corresponding interval 13, then the terminal 331is maintained at the higher level. If the strobe signal 181 assumes thehigher level in response to the interval 13, the NAND gate 330 isenabled to maintain its output terminal 332 at the lower level.Accordingly, the state of the first memory circuit is changed so thatthe output terminals 321 and 311 are maintained respectively at thehigher and lower level. And this state is maintained even after thetime-shared interval 13 has passed away, since both the signal at theoutput terminal 332 and the reset signal 151 assume the higher level.The levels at the terminals 321 and 311 are transferred respectively tothe NAND gates 370 and 360 forming the second memory circuit through theNAND gates 340 and 350 opened by the transfer signal 171 generatedduring the time-shared interval 99. Namely, the very signal appearing atthe terminal 311 when the transfer signal 171 is on the point of beinggenerated, appears at the output terminal 361. This is true also for theterminals 321 and 371. The state of the second memory circuit ismaintained until the next pulse of the transfer signal 171 has arrived.

FIG. 12 illustrates an exemplary circuit diagram of the restoring block6 comprising eight equivalent units, one of which is illustrated in FIG.10. Here, the fault detecting circuit 400 is not shown. In theconstitution of the restoring block 6 shown in FIG. 12, the reset signal151, the level signal 124, the strobe signal 181 and the transfer signal171 are applied respectively with the input busses common to the eightunits.

A plurality of receivers may be introduced in place of one and in thiscase the time-shared intervals in use have to be allocated appropriatelyto the plural receivers. FIG. 13 shows a case where two receivers areconnected with one transmitter. This is usual, for example, with theapplication to an automobile in which it is required to controllablyenergize the front search light and the tail lamps by a manual switchactuated by the driver. In such a case, the transmitter is placed withinthe drivers reach and the two receivers are placed within the engineroom and the trunk room and the wired OR method using DTL may beresorted to.

The fault detecting circuit 400 used in the abovedescribed multiplexsignal transmission system to forci bly prevent the actuation of theloads under fault conditions resulting from the grounding of the levelsignal line, that is, under abnormal conditions where the loads tend tobe actuated irrespective of the presence or absence of commands, willnow be described with reference to FIG. 14. The fault detecting circuitshown in FIG. 14 is adapted for incorporation in the previouslydescribed restoring block 6 and it receives the transmitted level signal124 as well as the actuation command signal restored in the restoringblock 6 and applied to the terminal 361 shown in FIG. 11. In FIG. 14-,the letter R designates a resistor, C a capacitor, 4111 an invertinggate, 420 a NOR gate, 430 a load.

When the level signal 124 which becomes abnormal at a point a in FIG.15A by the grounding of the level signal line is introduced to the faultdecting circuit 400, the waveform shown in FIG. 15B is generated at aterminal RC by the integrator circuit comprising the capacitor C and theresistor R and the waveform shown in FIG. 15C appears at an outputterminal 421 of the inverting gate 410. In other words, the l levelsignal appears upon the occurrence of the fault at the point a. Whenthis occurs, irrespective of the signal state of the actuation commandsignal for actuating the load 430 which is applied to the terminal 361,a signal appears at the output of the NOR gate 420 to forcibly preventthe actuation of the load 4311. When the level signal 124 returns to thenormal state, the signal at the output terminal 421 of the invertinggate 410 changes to 0 and therefore the inverted signal of the appliedsignal at the terminal 36! appears at the output of the NOR gate 420.This signal determines whether the load 430 should be actuated or not.

FIG. 16 illustrates another embodiment of the fault detecting circuit inthe device of this invention which includes memory circuits. The faultdetecting circuit of FIG. 16 receives, for example, the multiplexcommunication level signal 124 as well as the reset signal 151 and thetransfer signal 171 generated by the circuit shown in FIG. 10 and italso receives as in the embodi ment of FIG. 3 the load actuating commandsignal applied to the terminal 361.

When the level signal 124 which becomes abnormal by the grounding of thelevel signal line at the point a in FIG. 17A is applied to the circuit,it is inverted by an inverting gate 410a to produce at a terminal 411the waveform shown in FIG. 17B. This waveform is applied to the input111 of a set-reset type flip-flop memory circuit comprising NAND gates4111c and 411M. The other input of this flip-flop receives the invertedwaveform of the reset signal 151 shown in FIG. 17C. Consequently, thewaveforms shown in FIGS. 17E and 17F appear respectively at flip-flopoutput terminals 412 and 413. The logical products of these outputwaveforms with the transfer signal 171 shown in FIG. 17D are produced byNAND gates 410e and 41m" so that the waveforms shown in FIGS. 17G and171-] are produced at their respective output terminals 414 and 415.These output waveforms are applied to the respective inputs of thesecond stage set-reset type flip-flop memory circuit comprising NANDgates 410g and 41% to produce the waveform shown in FIG. 17I at aflip-flop output terminal 421. In other words, if the level signal 124becomes abnormal at the point a in FIG. 17A, then the abnormal levelsignal which changes to 1 upon the arrival of the first l level pulse ofthe transfer signal 171 shown in FIG. 17D appears at the output terminal421 and this abnormal signal is applied to the NOR gate 420. When thisabnormal 1" level signal is present at the NOR gate 420, irrespective ofthe introduction of the actuation command signal for actuating the load430 applied to the terminal 361, the signal at the output of the NORgate 420 changes to O to forcibly prevent the actuation of the load 43.In this way, when a fault condition occurs as a result of the groundingof the level signal line, any erroneous operation of the loads can beprevented. Further, the above-mentioned flip-flops are not limited tothe set-reset type, but they may be of the J-K type or the D-type.

I claim: a

1. In a multiplex signal transmission system comprising a transmitterfor generating a synchronous signal, a timing signal and a level signalhaving information to be transmitted superposed on the designatedaddresses, and a receiver including signal generating means forreceiving said signals to generate a reset signal and a transfer signal,and restoring means for receiving said reset signal, said transfersignal and said level signal to generate an actuation signal, a faultdetecting circuit comprising detecting means for generating a signal bydetecting the fact that said level signal has superposed information onall the addresses, and means connected to said restoring means to blocksaid actuation signal upon the generation of said detected signal.

2. A fault detecting circuit according to claim 1, wherein saiddetecting means comprises an integrator circuit.

3. A fault detecting circuit according to claim 1, wherein saiddetecting means comprises a first flip-flop circuit having a firstterminal for receiving said level signal and a second terminal forreceiving said reset signal, two logic circuits each thereof having afirst input terminal connected to said first flip-flop circuit and asecond input terminal for receiving said transfer signal, and a secondflip-flop circuit connected to said logic circuits.

1. In a multiplex signal transmission system comprising a transmitterfor generating a synchronous signal, a timing signal and a level signalhaving information to be transmitted superposed on the designatedaddresses, and a receiver including signal generating means forreceiving said signals to generate a reset signal and a transfer signal,and restoring means for receiving said reset signal, said transfersignal and said level signal to generate an actuation signal, a faultdetecting circuit comprising detecting means for generating a signal bydetecting the fact that said level signal has superposed information onall the addresses, and means connected to said restoring means to blocksaid actuation signal upon the generation of said detected signal.
 2. Afault detecting circuit according to claim 1, wherein said detectingmeans comprises an integrator circuit.
 3. A fault detecting circuitaccording to claim 1, wherein said detecting means comprises a firstflip-flop circuit having a first terminal for receiving said levelsignal and a second terminal for receiving said reset signal, two logiccircuits each thereof having a first input terminal connected to saidfirst flip-flop circuit and a second input terminal for receiving saidtransfer signal, and a second flip-flop circuit connected to said logiccircuits.